From: slack <slack@codemaniacs.com>
Date: Fri, 12 Sep 2008 01:56:55 +0000 (+0200)
Subject: Added missing 'SBC A,inm' opcode implementation :P
X-Git-Tag: v0.1~9
X-Git-Url: http://slack.codemaniacs.com/git/?a=commitdiff_plain;h=38a8ffb28c8d1f48f900057d2d7e94e05e09f394;p=wenboi.git

Added missing 'SBC A,inm' opcode implementation :P
---

diff --git a/gbcore.cc b/gbcore.cc
index 4526935..a208899 100644
--- a/gbcore.cc
+++ b/gbcore.cc
@@ -694,8 +694,25 @@ GameBoy::run_status GameBoy::run_cycle()
 
 					case 0x9E: {//SBC (HL)
 						int carry = (check_flag(CARRY_FLAG)? 1 : 0);
-						int res = regs.A - memory.read(regs.HL) - carry;
-						int half_res = (regs.A & 0x0F) - (memory.read(regs.HL) & 0x0F) - carry;
+						int val = memory.read(regs.HL);
+						int res = regs.A - val - carry;
+						int half_res = (regs.A & 0x0F) - (val & 0x0F) - carry;
+						regs.A = static_cast<u8>(res);
+
+						set_flag(ADD_SUB_FLAG);
+						set_flag_if (res < 0,      CARRY_FLAG);
+						set_flag_if (res == 0,     ZERO_FLAG);
+						set_flag_if (half_res < 0, HALF_CARRY_FLAG);
+						cycles_until_next_instruction = 8; 
+						break;
+						}
+
+					// SBC inm
+					case 0xDE: {
+						int carry = (check_flag(CARRY_FLAG)? 1 : 0);
+						int inm = memory.read(regs.PC++);
+						int res = regs.A - inm - carry;
+						int half_res = (regs.A & 0x0F) - (inm & 0x0F) - carry;
 						regs.A = static_cast<u8>(res);
 
 						set_flag(ADD_SUB_FLAG);
@@ -706,7 +723,6 @@ GameBoy::run_status GameBoy::run_cycle()
 						break;
 						}
 
-					// There is no SBC inm
 
 					// AND n
 					for_each_register(0xA7, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, AND_reg)
diff --git a/wendi/disasm.cc b/wendi/disasm.cc
index 11f201f..a68f060 100644
--- a/wendi/disasm.cc
+++ b/wendi/disasm.cc
@@ -279,6 +279,7 @@ Instruction disassemble_opcode(GameBoy &gb, u16 addr)
 		dis_for_each_register(0x9F, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, "SBC", Instruction::ALU, dis_reg)
 
 		dis__reg16_(0x9E, "SBC", Instruction::ALU, HL)
+		dis_reg_inm(0xDE, "SBC", Instruction::ALU, A)
 
 		// AND n
 		dis_for_each_register(0xA7, 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, "AND", Instruction::ALU, dis_reg)